1. Field of the Invention
The present invention is related to bus architecture of computer systems, and more particularly, to a bus architecture for a multiprocessor computer system.
2. Description of the Related Art
A common technique for increasing computing power in a computer system is to increase the number of processors in the system. Multidrop, bus-oriented networks for connecting multiple processors are generally less complex and more easily adapted to existing software than point-to-point systems which require a significant investment in low level software designed for the specific network. Known bus architectures of this type include Multibus II from INTEL CORP., Futurebus from the IEEE P896.1 working group, PI Bus from the Pave Pillar initiative, Fastbus from the USNIM Committe of the DOE, VME from Motorola, and NU-BUS from Texas Instruments. However, these and other known multiprocessor bus architectures have several limitations on the number of processors which can be connected together.
When some or all of the memory in the computer system is shared, the processors are considered "tightly coupled" and programming the computer system can be simplified. However, tight coupling requires a large bandwidth between the processors and the memories to be effective. Typically, three or four processors can share memory in this fashion to triple or quadruple the processing power of the computer system. However, as a fifth or sixth processor is added to the system, there are increasingly smaller additions to computing power because the processors spend too much of their time waiting for access to the bus. In addition, increasing the number of processors and other units in the computer system increase the electrical load on the bus, further limiting performance.
Some of the multiprocessor bus architectures include two buses, primarily to provide redundancy. Other bus architectures group the processors in clusters using a hierarchy of buses. However, the number of processors at the lowest hierarchy level is still limited to approximately four for maximum efficiency.
Increasing the number of buses results in an increased number of connections to each circuit card, requiring that each card has a minimum size to provide room for the necessary connections. If the number of bits transmitted on each bus is reduced, the number of buses can be increased without affecting the physical size limitation; however, the bandwidth of each bus is reduced.